1. Field of the Invention
The present invention relates to a large scale FIFO (i.e., large scale integration First In First Out) circuit in which a shift register circuit constructed of a plurality of flip-flop circuits performs address generation. More particularly, the present invention relates to a large scale FIFO circuit which is capable of reducing its entire size by reducing the occupation area size of the shift register circuit.
Further, the present invention relates to a large scale FIFO circuit capable of temporary storing data in a memory when the data is low in processing speed. The large scale FIFO circuit is also capable of outputting the thus processed data from the memory at high speed in order of completion of such processing of the data.
2. Description of the Related Art
As shown in FIG. 5, the large scale FIFO circuit of this type is used extensively in each of: a shift resister circuit 51-W which assigns memory locations of a memory 50 to input data Din being stored therein; and, a shift resister circuit 51-R which identifies the memory locations of the memory 50 from which output data Dout is sequentially retrieved.
Heretofore, as shown in FIG. 6, in this type of the large scale FIFO circuit, for example, with respect to addresses of 16 words, 16 pieces of the flip flop (hereinafter referred to as the F/F) circuits 100 to 115 are used to form a shift register circuit. These F/F circuits 100 to 115 are connected in series with each other, wherein an output signal of the last F/F circuit 115 is inputted to the first F/F circuit 100 to provide a loop arrangement in the F/F circuits 100 to 115. Further, the same clock (hereinafter referred to as the CLK) signal is applied to the CLK terminals of these F/F circuits 100 to 115. Each of addresses 0 to 15 corresponds to an output signal of each of the corresponding F/F circuits 100 to 115, and, therefore supplies such output signal therefrom.
Consequently, in a condition in which shift data stays in the address 0 at a time of occurrence of a first CLK signal, when a second CLK signal is inputted to tall the CLK terminals of the F/F circuits 100 to 115, the shift data is shifted to the address 1. When a third CLK signal is inputted to all the CLK terminals of the F/F circuits 100 to 115, the shift data further is shifted to the address 2. In this way, the shift data is successively shifted from one address to another address which is successive to such one address when the successive CLK signal is inputted to the CLK terminals of the F/F circuits 100 to 115.
In the conventional large scale FIFO circuit just described above, the number of stages of the F/F circuits which form the shift register circuit is large, so that the shift register circuit is large in occupation area size, which increases the entire size of the FIFO circuit, and, therefore presents a problem.
The reason why the entire size of the FIFO circuit increases is that the number of stages of the F/F circuits forming the shift register circuit is directly depending on the number of words, i.e., size of a memory to which the F/F circuits are directed. For example, in the case of small 32 words, a necessary number of stages of the F/F circuits is only 32. However, in the case of, for example, large 1000 words, a necessary number of stages of the F/F circuits becomes a very large number such as 1024. Due to this, the entire size of the FIFO circuit increases.
It is accordingly an object of the present invention to solve the above problem by providing a large scale FIFO circuit, the entire size of which FIFO circuit is reduced by reducing a shift register circuit in its occupation area size.
According to a first aspect of the present invention, there is provided a large scale FIFO circuit in which address generation is performed by a shift register circuit constructed of a plurality of flip flop circuits, the improvement wherein:
the shift register circuit is divided into a plurality of small scale shift register circuits each constructed of a plurality of the flip flop circuits; and
the address is defined by combination of outputs of the flip flop circuits which form each of the small scale shift register circuits.
According to a second aspect of the present invention, there is provided a large scale FIFO circuit in which address generation is performed by the shift register circuit constructed of a plurality of the flip flop circuits:
a plurality of small scale shift register circuits each constructed of a plurality of the flip flop circuits are formed;
an input clock signal is supplied to a first one of the small scale shift register circuits;
of the remaining ones of the small scale shift register circuits, one has its address output signal supplied to its successors as a clock input signal by cascading the remaining small scale register circuits in connection;
the number of addresses in the address generation is divided by a positive integer, which integer forms a first factor of the number of the addresses, to produce a plurality of second factors of the number of the addresses;
the number of the flip flop circuits in each of the small scale shift register circuits is equal to the number of each of the second factors of the number of the addresses;
an input clock signal is supplied to a first one of the small scale shift register circuits; and
of the remaining ones of the small scale shift register circuits, one has its address output signal supplied to its successor as a clock input signal by cascading the remaining small scale register circuits in connection.
Due to the above construction, it is possible that the large scale FIFO circuit is constructed of a plurality of thus divided small scale shift register circuits. This reduces the number of the flip flop circuits forming the shift register circuit. Since the shift register circuit is reduced in size, it is possible to reduce the entire size of the FIFO circuit.
A preferable mode for practicing the present invention has the following construction: namely
In a large scale FIFO circuit in which: address generation is performed by a shift register circuit constructed of a plurality of flip flop circuits; and, addresses in the address generation identify memory locations of a memory in each of a read and a write side of the memory, the memory having an address space for a plurality of words the number of which is N, the improvement wherein:
the N is divided into its factors A and B (i.e., N=A xc3x97B; where each of N, A and B is a positive integer);
with respect to each of the factors A and B, each of a plurality of small scale register circuits is formed;
an input clock signal is supplied to one of the small scale shift register circuits, which one corresponds to the factor A to supply an output signal to the other of the small scale shift register circuits as a clock signal therefor, the other corresponding to the factor B.
In this case, in each of the read and the write side, it is possible for the shift register circuit to reduce the number of N pieces of the conventional flip flop circuits up to (A+B) pieces.
Further, when each of the small scale shift register circuits is of the same circuit scale, it is possible for the large scale FIFO circuit to be a minimum size in construction.
The reason why it is possible to reduce the shift register circuits in their occupation area size and to reduce the entire size of the FIFO circuit is that: addressing or address setting is performed by combination of a plurality of addresses, which addresses are generated by sequentially cascading the small scale shift register circuits, wherein: the number of necessary addresses is divided to form a plurality of small scale shift register circuits; an external input clock signal is supplied to only one of the small scale shift register circuits; and, of the remaining ones of the small scale shift register circuits, one has its output signal supplied to its successor as a clock input signal by cascading these small scale shift register circuits.